In this paper, a low power, scalable sorting network is designed by integrating a Gate Diffusion Input (GDI) - based magnitude comparator and an enhanced weighted bitstream converter. The bit-stream converter is extended to support 4-bit, 8-bit, 16-bit and 32-bit inputs, generating accurate weighted bit-streams in just n clock cycles instead of 2n. The magnitude comparator from the sorting block is redesigned using GDI logic to significantly reduce power consumption compared to conventional CMOS logic, Power and delay metrics are evaluated under identical conditions.

A low-power 32-bit Binary-Coded Decimal (BCD) adder based on the Carry Lookahead Adder (CLA) architecture. It is designed for high-speed and power-efficient operation. The design targets applications that need precise decimal computation, such as financial and embedded systems. To reduce power consumption, it uses Power Gating, which lowers leakage current by turning off inactive circuit blocks. Power Gating performs better than Clock Gating when it comes to reducing leakage power, especially in wider data-path designs. The architecture is modeled in Verilog HDL, simulated with Xilinx Vivado and implemented on an FPGA platform for functional testing. Results show considerable improvements in power efficiency and operational speed, confirming that the CLA-Power Gating approach is suitable for low-power VLSI arithmetic units.